Memory Layout Design Engineer

Must have transistor, cell and block level memory layout design hands on experience in either of 3nm/5nm/7nm/10nm/14nm FinFET process technology ...

For full details including how to apply please visit neuvoo.ca/job.php?id=504a0854fd8b&source=madgex_eic&utm_source=partner&utm_medium=madgex_eic&puid=gddb8ddg1dbcbadfdddgad981dbbedac3aea7adccdd8aade8ed3fddfbddeeed3gbdbabddfcdc3e (the link will open in a new window)